In semiconductor fabrication, various layers of insulating material, semiconducting material and conducting material are formed to produce a multilayer (multilevel) semiconductor device. The layers are patterned to create features that taken together, form elements such as transistors, capacitors, and resistors. These elements are then interconnected to achieve a desired electrical function, thereby producing an integrated circuit (IC) device. The formation and patterning of the various device layers may be accomplished using various fabrication techniques including oxidation, implantation, deposition, epitaxial growth of silicon, lithography, etching, and planarization.
Since the introduction of semiconductor devices, the size of semiconductor devices has been continuously shrinking, resulting in smaller semiconductor chip size and increased device density. One of the limiting factors in the continuing evolution toward smaller device size and higher density has been signal delay caused by parasitic capacitive effects of insulating materials in which metal interconnects are formed to interconnect devices. It has become necessary to reduce the capacitance of insulating layers by allowing insulating layer thicknesses to shrink along with other device features such as metal interconnect line widths. As a result, the need for lower dielectric constant materials has resulted in the development of several different types of organic and inorganic low-k materials.
Manufacturing processes such as, for example, damascene processes, have been implemented to form metallization vias and interconnect lines (trench lines) by dispensing entirely with the metal etching process. The damascene process is a well known semiconductor fabrication method for forming multiple levels of metallization vias and interconnect lines (trench lines). For example, in the dual damascene process, a trench opening and via opening are etched in an insulating layer also known as an inter-metal or inter-level dielectric (IMD/ILD) layer. The insulating layer is typically formed over a substrate including another conductive area over which the vias and trench lines are formed and in communication with. After a series of photolithographic steps defining via openings and trench openings, the via and the trench openings are filled with a metal, preferably copper, to form metallization vias and interconnect lines (trench lines), respectively. The excess metal above the trench line level is then removed by well known chemical-mechanical planarization (polishing) (CMP) processes.
As indicated, advances in semiconductor device processing technology demands the increasing use of low-k (low dielectric constant) insulating materials in, for example, IMD (ILD) layers that make up the bulk of a multilayer device. In order to reduce signal delays caused by parasitic effects related to the capacitance of insulating layers, for example, IMD layers, incorporation of low-k materials has become standard practice as semiconductor feature sizes have diminished. Many of the low-k materials are designed with a high degree of porosity to allow the achievement of lower dielectric constants. Several different organic and inorganic low-k materials have been developed and proposed for use in semiconductor devices as insulating material having dielectric constants less than about 3.0 for achieving integration of, for example, 0.13 micron interconnections. In the future, even lower dielectric constant material, for example less than about 2.5, will be required for 0.1 micron process integration, and dielectric constants of less than about 2.0 will be required for 0.07 micron process integration.
One exemplary low-k inorganic material that is frequently used, for example, is carbon doped silicon dioxide (C-oxide) formed by a CVD process where the dielectric constant may be varied over a range depending on the process conditions. Carbon doped oxide, for example, may be formed with dielectric constants over a range of about 2.0 to about 3.0 and density of about 1.3 g/cm3 compared to dielectric constants of about 4.1 and a density of about 2.3 g/cm3 for silicon dioxides (e.g., un-doped TEOS). Other exemplary low-k inorganic materials include porous oxides, xerogels, or SOG (spin-on glass). Exemplary low-k organic materials include polysilsequioxane, parylene, polyimide, benzocyclobutene and amorphous Teflon.
One problem with low-k materials is that frequently during semiconductor processing, including chemical mechanical polishing (CMP), plasma etching, and isotropic wet etching processes, the surface of the low-k material is damaged. The damage to the surface of the low-k material can significantly alter the surface dielectric constant resulting in a relatively higher dielectric constant at the surface compared to the bulk. There are presently available various methods to obtain the bulk dielectric constant of low-k insulating layer by passing an electric field through the bulk of the low-k material to measure the bulk capacitance of the low-k material.
For example, one method to measure bulk capacitance during semiconductor device manufacture is to fabricate on the wafer a large capacitor having a value in excess of 1 picofarad. A capacitor of this size is necessary because of the various stray capacitances which exist in and on the wafer and which are measured along with the test capacitance. One plate of the capacitor under test is coupled to at least one large “testing” contact or pad to allow a test probe to access the capacitor.
However, bulk capacitance measurement methods involve time consuming ex-situ measurements and it is not possible to reliably extract surface dielectric constant information using such methods. Surface dielectric constant information is useful including use of a non-destructive probe to optimize the various semiconductor manufacturing processes in order to minimize adverse effects on low-k material surfaces. In addition, methods for quickly and easily obtaining the surface dielectric constants, for example, in-situ, would increase cycle times and throughput in semiconductor wafer manufacturing.
There is therefore a need in the semiconductor processing art to develop a method and apparatus for determining the surface dielectric constant of low-k material layers whereby a semiconductor wafer process surface condition may be quickly and readily obtained.
It is therefore an object of the invention to provide a method and apparatus for determining the surface dielectric constant of low-k material layers whereby a semiconductor wafer process surface condition may be quickly and readily obtained while overcoming other shortcomings and deficiencies of the prior art.